From: Segher Boessenkool Date: Fri, 3 Nov 2017 14:09:10 +0000 (+0100) Subject: rs6000: Improve *lt0 patterns X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=187bd6cd5e46e3b51aecd537582b146ccb6f21bd;p=gcc.git rs6000: Improve *lt0 patterns The rs6000 port currently has an *lt0_disi define_insn, setting the DI result to whether the SI argument is negative or not. It turns out the generic optimisers cannot always figure out in the other cases either that this is just a shift for us. This patch adds patterns for all four SI/DI combinations. * config/rs6000/rs6000.md (*lt0_disi): Delete. (*lt0_di, *lt0_si): New. From-SVN: r254374 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e8ebe14f133..561e3dae7c9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-11-03 Segher Boessenkool + + * config/rs6000/rs6000.md (*lt0_disi): Delete. + (*lt0_di, *lt0_si): New. + 2017-11-03 Segher Boessenkool * config/rs6000/rs6000.md (move_from_CR_ov_bit): Change condition to diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3ad702daa06..2ef028f93b3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3829,11 +3829,19 @@ ; Special case for less-than-0. We can do it with just one machine ; instruction, but the generic optimizers do not realise it is cheap. -(define_insn "*lt0_disi" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (lt:DI (match_operand:SI 1 "gpc_reg_operand" "r") - (const_int 0)))] +(define_insn "*lt0_di" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lt:GPR (match_operand:DI 1 "gpc_reg_operand" "r") + (const_int 0)))] "TARGET_POWERPC64" + "srdi %0,%1,63" + [(set_attr "type" "shift")]) + +(define_insn "*lt0_si" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (lt:GPR (match_operand:SI 1 "gpc_reg_operand" "r") + (const_int 0)))] + "" "rlwinm %0,%1,1,31,31" [(set_attr "type" "shift")])