From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 16 Jul 2022 09:51:36 +0000 (+0100)
Subject: add checklist for adding instructions
X-Git-Tag: opf_rfc_ls005_v1~1181
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=188f64e39421129af1b2be4c3264476b4115f380;p=libreriscv.git

add checklist for adding instructions
---

diff --git a/docs.mdwn b/docs.mdwn
index de8dceec0..8b3147aee 100644
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -69,3 +69,13 @@ yourself, in order to verify them, see [[HDL_workflow]]
 
 Currently in Draft form, [[openpower/sv/svp64]] is the basis of the
 Supercomputing Cray-style Vectorisation of the Power ISA.
+
+## Checklist for adding an instruction
+
+TODO.  use the commit diffs for these instructions as a guide
+
+* fmvis <https://bugs.libre-soc.org/show_bug.cgi?id=887>
+* avgadd etc. <https://bugs.libre-soc.org/show_bug.cgi?id=863>
+* int min/max <https://bugs.libre-soc.org/show_bug.cgi?id=234#c1>
+* ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745> which included
+  adding a hardware implementation as well