From: Giacomo Travaglini Date: Tue, 11 Aug 2020 13:11:29 +0000 (+0100) Subject: arch-arm: Disable HVC when SCR_EL3.HCE is 0 X-Git-Tag: v20.1.0.0~311 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18993204620cf18755442d09f6b852cbff455c04;p=gem5.git arch-arm: Disable HVC when SCR_EL3.HCE is 0 This was already implemented for AArch32 but it had been wrongly removed by: https://gem5-review.googlesource.com/c/public/gem5/+/31394 Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32636 Tested-by: kokoro --- diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 3ee0d618f..5439baae6 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -119,12 +119,15 @@ let {{ exec_output += PredOpExecute.subst(smcIop) hvcCode = ''' + HCR hcr = Hcr; CPSR cpsr = Cpsr; + SCR scr = Scr; // Filter out the various cases where this instruction isn't defined if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) || (cpsr.mode == MODE_USER) || - (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase()))) { + (isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) || + (ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) { fault = disabledFault(); } else { fault = std::make_shared(machInst, imm);