From: lkcl <lkcl@web>
Date: Thu, 11 May 2023 17:25:47 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18a8e87e85bc6eef0a8665ebb53cfba1213c46dd;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c15ba9cfd..498c68d7e 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -152,7 +152,10 @@ processing of large Vector operations, only under the condition
 that partial results are cleanly discarded, and continuation on return
 from the Trap Handler will restart the entire operation.
 The reason is that saving of full Architectural State is
-not practical.
+not practical. An example would be a Floating-Point Horizontal Sum instruction
+(very common in Vector ISAs) or a Dot Product instruction
+that specifies a higher degree of accuracy for the *internal*
+accumulator than the registers.
 
 Simple-V operates on an entirely different paradigm from traditional
 Vector ISAs: as a Sub-Program Counter where "Elements" are synonymous
@@ -200,17 +203,29 @@ calculations.
 An additional caveat involves Condition Register Fields
 when also used as Predicate Masks. An operation that
 overwrites the same CR Fields that are simultaneously
-being used as a Predicate Mask is `UNDEFINED` behaviour
+being used as a Predicate Mask should exercise extreme care
 if the overwritten CR field element was needed by a
 subsequent Element for its Predicate Mask bit.
-This allows implementations to relax some of the
-otherwise-draconian Register Hazards that would otherwise
-occur, and to consider internal cacheing of the CR-based
-Predicate
-bits, but some implementations *may not necessarily
-perform pre-reading* and consequently the risk of
+
+Some implementations may deploy Cray's technique of
+"Vector Chaining" (including in this case reading the CR field
+containing the Predicate bit until the very last moment),
+and consequently avoiding the risk of
 overwrite is the responsibility of the Programmer.
-Special care is particularly needed here when using REMAP.
+`hphint` may be used here to good effect.
+Extra Special care is particularly needed here when using REMAP
+and also Vertical-First Mode.
+
+The simplest option is to use Integer Predicate Masks but the
+caveats are stricter:
+
+* In Vertical-First loops Programmers **must not** write to any
+  Integers (r3, r0, r31) used as Predicate Masks. Doing so
+  is `UNDEFINED` behaviour.
+* An **entire** Vector is held up on Horizontal-First Mode if the
+  Integer Predicate is still in in-flight Reservation Stations
+  or pipelines.  Only Speculative Vector Chaining mitigates delays
+  but can be wasteful of resources.
 
 ## Register files, elements, and Element-width Overrides