From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 10 Feb 2020 20:39:54 +0000 (+0000)
Subject: document partsig operators
X-Git-Tag: ls180-24jan2020~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18ab7b40bba5992ace634de8eeab86330f945002;p=ieee754fpu.git

document partsig operators
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 157ea35f..5977bca6 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -273,6 +273,7 @@ class PartitionedSignal:
             ``1`` if an odd number of bits are set, ``0`` if an
                   even number of bits are set.
         """
+        # XXXX TODO: return partition-mask-sized set of bits
         raise NotImplementedError
         return Operator("r^", [self])
 
@@ -285,4 +286,5 @@ class PartitionedSignal:
             ``0`` if ``premise`` is true and ``conclusion`` is not,
             ``1`` otherwise.
         """
+        # amazingly, this should actually work.
         return ~premise | conclusion