From: Michael Nolan <mtnolan2640@gmail.com>
Date: Mon, 11 May 2020 14:28:28 +0000 (-0400)
Subject: Fix rlwimi by reordering the inputs *again*
X-Git-Tag: div_pipeline~1283
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18bc55100db0b23d48277b43b108207e96242f06;p=soc.git

Fix rlwimi by reordering the inputs *again*
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 9d44730d..faad0eb5 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -26,14 +26,14 @@ def get_rec_width(rec):
 
 def set_alu_inputs(alu, dec2, sim):
     inputs = []
-    reg1_ok = yield dec2.e.read_reg1.ok
-    if reg1_ok:
-        reg1_sel = yield dec2.e.read_reg1.data
-        inputs.append(sim.gpr(reg1_sel).value)
     reg3_ok = yield dec2.e.read_reg3.ok
     if reg3_ok:
         reg3_sel = yield dec2.e.read_reg3.data
         inputs.append(sim.gpr(reg3_sel).value)
+    reg1_ok = yield dec2.e.read_reg1.ok
+    if reg1_ok:
+        reg1_sel = yield dec2.e.read_reg1.data
+        inputs.append(sim.gpr(reg1_sel).value)
     reg2_ok = yield dec2.e.read_reg2.ok
     if reg2_ok:
         reg2_sel = yield dec2.e.read_reg2.data
@@ -189,7 +189,6 @@ class ALUTestCase(FHDLTestCase):
             with Program(lst) as program:
                 sim = self.run_tst_program(program, initial_regs)
 
-    @unittest.skip("broken")
     def test_rlwimi(self):
         lst = ["rlwimi 3, 1, 5, 20, 6"]
         initial_regs = [0] * 32