From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 1 Apr 2020 03:23:14 +0000 (-0700)
Subject: add test case for https://github.com/nmigen/nmigen/issues/344
X-Git-Tag: 24jan2021_ls180~74
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18c2dc9b791eb04d9205d5fc98f1eb909c469e69;p=nmutil.git

add test case for https://github.com/nmigen/nmigen/issues/344
---

diff --git a/src/test_run_simulation_bug.py b/src/test_run_simulation_bug.py
new file mode 100644
index 0000000..df4bb89
--- /dev/null
+++ b/src/test_run_simulation_bug.py
@@ -0,0 +1,30 @@
+from nmigen import Signal, Module, Elaboratable
+from nmigen.compat.sim import run_simulation
+
+# test for https://github.com/nmigen/nmigen/issues/344
+
+
+class MyModule(Elaboratable):
+    def __init__(self):
+        self.a = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.a.eq(~self.a)
+        return m
+
+
+def test1():
+    dut = MyModule()
+
+    def generator():
+        for _i in range(10):
+            print((yield dut.a))
+            yield
+
+    run_simulation(dut, generator(),
+                   vcd_name="test_run_simulation_bug.vcd")
+
+
+if __name__ == '__main__':
+    test1()