From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Oct 2014 09:49:31 +0000 (+0200)
Subject: Don't be too smart with $dff cells with "init" attribute on out signal
X-Git-Tag: yosys-0.4~44
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18cb8b4636933cb5a1ad3040f061d53345d1aa1d;p=yosys.git

Don't be too smart with $dff cells with "init" attribute on out signal
---

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index c7e92ddc1..5f52bb8d8 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -83,7 +83,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
 		val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
 	}
 
-	if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
+	if (dff->type == "$dff" && mux_drivers.has(sig_d) && !has_init) {
 		std::set<RTLIL::Cell*> muxes;
 		mux_drivers.find(sig_d, muxes);
 		for (auto mux : muxes) {