From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 26 Sep 2020 17:30:24 +0000 (+0100)
Subject: make check of LDSTMode.update conditional in PowerDecoder2
X-Git-Tag: 24jan2021_ls180~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18cd7c75da484e6dd68eb97bd74d26cdbaef0f8a;p=soc.git

make check of LDSTMode.update conditional in PowerDecoder2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 5df3f16c..e24de8a3 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -369,10 +369,11 @@ class DecodeOut2(Elaboratable):
         m = Module()
         comb = m.d.comb
 
-        # update mode LD/ST uses read-reg A also as an output
-        with m.If(self.dec.op.upd == LDSTMode.update):
-            comb += self.reg_out.eq(self.dec.RA)
-            comb += self.reg_out.ok.eq(1)
+        if hasattr(self.dec.op, "upd"):
+            # update mode LD/ST uses read-reg A also as an output
+            with m.If(self.dec.op.upd == LDSTMode.update):
+                comb += self.reg_out.eq(self.dec.RA)
+                comb += self.reg_out.ok.eq(1)
 
         # B, BC or BCREG: potential implicit register (LR) output
         # these give bl, bcl, bclrl, etc.