From: Nicholas Calderwood <nicholas@libre-soc.org>
Date: Sat, 14 Oct 2023 14:31:06 +0000 (+0100)
Subject: add english to lhzupx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18ddff437de29be6e81d4cb2d4fb28b0de66b35f;p=openpower-isa.git

add english to lhzupx instruction
---

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index f67107fe..ab2477bc 100644
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -98,6 +98,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- (RA) + (RB)
 
+Description:
+
+    Let the effective address (EA) be register RA.
+    The halfword in storage addressed by EA is loaded into
+    RT[48:63]. RT[0:47] are set to 0.
+
+    The sum (RA) + (RB) is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None