From: Luke Kenneth Casson Leighton Date: Sun, 3 Jun 2018 15:11:51 +0000 (+0100) Subject: add images X-Git-Tag: convert-csv-opcode-to-binary~5306 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18e254c26f2c46d25a7ad6dde8d06069f30bffc1;p=libreriscv.git add images --- diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 1ca0cab71..c100bdf41 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -366,8 +366,8 @@ for (int i = 0; i < VL; ++i) \item key is int regfile number or FP regfile number (1 bit)\vspace{6pt} \item register to be predicated if referred to (5 bits, key)\vspace{6pt} \item register to store actual predication in (5 bits, value)\vspace{6pt} - \item predication is inverted (1 bit)\vspace{6pt} - \item non-predicated elements are to be zero'd (1 bit)\vspace{6pt} + \item predication is inverted Y/N (1 bit)\vspace{6pt} + \item non-predicated elements are to be zero'd Y/N (1 bit)\vspace{6pt} \end{itemize} Notes:\vspace{10pt} \begin{itemize}