From: Luke Kenneth Casson Leighton Date: Tue, 8 Jan 2019 09:03:41 +0000 (+0000) Subject: add overview to requirements spec X-Git-Tag: convert-csv-opcode-to-binary~4759 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18e8dd479a3212f57184cc8fae0c5d0e10bf8f83;p=libreriscv.git add overview to requirements spec --- diff --git a/3d_gpu/requirements_specification.mdwn b/3d_gpu/requirements_specification.mdwn index a93d1c156..040d0d9e5 100644 --- a/3d_gpu/requirements_specification.mdwn +++ b/3d_gpu/requirements_specification.mdwn @@ -1,5 +1,14 @@ # Requirements Specification +This document contains the Requirements Specification for the Libre RISC-V +micro-architectural design. It shall meet the target of 5-6 32-bit GFLOPs, +150 M-Pixels/sec, 30 Million Triangles/sec, and minimum video decode +capability of 720p @ 30fps to a 1920x1080 framebuffer, in under 2.5 watts +at an 800mhz clock rate. Exceeding this target is acceptable if the +power budget is not exceeded. Exceeding this target just for the hell of +it is also acceptable, as long as it does not disrupt meeting the minimum +performance and power requirements. + # General Architectural Design Principle The general design base is to utilise an augmented and enhanced variant @@ -12,6 +21,13 @@ will all be added by overloading write hazards. An overview of the design is as follows: +* 3D and Video primitives (operations) will only be added as strictly + necessary to achieve the minimum power and performance target. +* Identified so far is a 4xFP32 ARGB Quad to 1xINT32 ARGB pixel + conversion opcode (part of the Vulkan API). It will write directly + to a separate "tile buffer" (SRAM), not to the integer register + file. The instruction will be scalar and will inherently and + automatically parallelised by SV, just like all other scalar opcodes. * The register files will be stratified into 4-way 2R1W banks, with byte-level write-enable on all banks. * 6600-style scoreboards will be augmented with "shadow" wires