From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 29 Sep 2019 18:25:34 +0000 (-0700)
Subject: FDCE_1 does not have IS_CLR_INVERTED
X-Git-Tag: working-ls180~881^2^2~203
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18ebb86edbade4a94833dead59d69fddd980f5bd;p=yosys.git

FDCE_1 does not have IS_CLR_INVERTED
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index ee9d48684..cf39bd45b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -408,7 +408,7 @@ module FDCE_1 (
   always @* Q = \$nextQ ;
 `else
   assign \$currQ = Q;
-  always @(negedge C, posedge CLR) if (CLR == !IS_CLR_INVERTED) Q <= 1'b0; else Q <= \$nextQ ;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
 `endif
 endmodule