From: Cole Poirier <colepoirier@gmail.com>
Date: Mon, 10 Aug 2020 16:05:53 +0000 (-0700)
Subject: mmu.py add line I forgot to translate from mmu.vhdl
X-Git-Tag: semi_working_ecp5~411
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18eebfeb76a9df381e10ea16fb3bf78576fe62bd;p=soc.git

mmu.py add line I forgot to translate from mmu.vhdl
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 8775652b..d5cba5a2 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -566,6 +566,7 @@ class AddrShifter(Elaboratable):
 #               pt_valid := r.pt3_valid;
             with m.Else():
                 comb += pgtbl.eq(r.pt3_valid)
+                comb += pt_valid.eq(r.pt3_valid)
 #           end if;
 
 #           -- rts == radix tree size, # address bits being translated