From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 12 Jun 2018 13:39:22 +0000 (+0200)
Subject: targets: change a7/k7ddrphy imports to s7ddrphy
X-Git-Tag: 24jan2021_ls180~1702
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=18f86881d9fb241417537f3fe175fa58efa31c51;p=litex.git

targets: change a7/k7ddrphy imports to s7ddrphy
---

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 1fdbfd5e..e074c47e 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT41K128M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy.mii import LiteEthPHYMII
 from liteeth.core.mac import LiteEthMAC
@@ -107,7 +107,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         self.add_constant("READ_LEVELING_BITSLIP", 3)
         self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K128M16(self.clk_freq, "1:4")
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 86ebe291..89498d67 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT8JTF12864
-from litedram.phy import k7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy import LiteEthPHY
 from liteeth.core.mac import LiteEthMAC
@@ -89,7 +89,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"))
         sdram_module = MT8JTF12864(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index ee13a6ef..fd33159c 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT47H64M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 
 class _CRG(Module):
@@ -93,7 +93,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         sdram_module = MT47H64M16(self.clk_freq, "1:4")
         self.register_sdram(self.ddrphy,
                             sdram_module.geom_settings,
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index b0265187..70e054ec 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -12,7 +12,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
 from litedram.modules import MT41K256M16
-from litedram.phy import a7ddrphy
+from litedram.phy import s7ddrphy
 
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
 from liteeth.core.mac import LiteEthMAC
@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
         self.submodules.crg = _CRG(platform)
 
         # sdram
-        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"))
         self.add_constant("READ_LEVELING_BITSLIP", 3)
         self.add_constant("READ_LEVELING_DELAY", 14)
         sdram_module = MT41K256M16(self.clk_freq, "1:4")