From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 31 Jan 2022 07:56:29 +0000 (+0100)
Subject: Fix scope
X-Git-Tag: yosys-0.14~2^2~15
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=190e44f0dac1a9c7f2dbf0c3069cd1d646806aaa;p=yosys.git

Fix scope
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 3cf5967cc..bea8f12b4 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -194,7 +194,7 @@ struct SimInstance
 			Module *mod = module->design->module(cell->type);
 
 			if (mod != nullptr) {
-				dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(module->name), mod, cell, this));
+				dirty_children.insert(new SimInstance(shared, scope + "." + RTLIL::unescape_id(cell->name), mod, cell, this));
 			}
 
 			for (auto &port : cell->connections()) {