From: Tim Newsome <tim@sifive.com>
Date: Sat, 23 Apr 2016 18:09:07 +0000 (-0700)
Subject: ROM -> RAM -> ROM, waiting for debug int.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=191671a2015136c429394fd3051e4a9c1ff45352;p=riscv-isa-sim.git

ROM -> RAM -> ROM, waiting for debug int.
---

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 16890cf..577edbb 100755
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -36,7 +36,7 @@ clear_debint:
 clear_debint_loop:
         csrr    s1, DCSR
         andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)
-        bnez    s1, wait_for_interrupt
+        bnez    s1, clear_debint_loop
 
         # Restore s1.
         csrr    s1, MCPUID
diff --git a/debug_rom/debug_rom.h b/debug_rom/debug_rom.h
index 96eb972..10c4fef 100644
--- a/debug_rom/debug_rom.h
+++ b/debug_rom/debug_rom.h
@@ -1,6 +1,6 @@
 static const unsigned char debug_rom_raw[] = {
   0x6f, 0x00, 0x40, 0x05, 0xf3, 0x24, 0x00, 0xf1, 0x23, 0x24, 0x90, 0x10,
-  0xf3, 0x24, 0x00, 0x79, 0x93, 0xf4, 0x04, 0x40, 0x63, 0x94, 0x04, 0x08,
+  0xf3, 0x24, 0x00, 0x79, 0x93, 0xf4, 0x04, 0x40, 0xe3, 0x9c, 0x04, 0xfe,
   0xf3, 0x24, 0x00, 0xf0, 0x63, 0xc6, 0x04, 0x00, 0x83, 0x24, 0xc0, 0xc3,
   0x6f, 0x00, 0x80, 0x01, 0x93, 0x94, 0x14, 0x00, 0x63, 0xc6, 0x04, 0x00,
   0x83, 0x34, 0x80, 0xc3, 0x6f, 0x00, 0x80, 0x00, 0x13, 0x00, 0x00, 0x00,
diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc
index 1d5c9ce..4d6df08 100644
--- a/riscv/gdbserver.cc
+++ b/riscv/gdbserver.cc
@@ -20,6 +20,25 @@
 #define C_EBREAK        0x9002
 #define EBREAK          0x00100073
 
+// Functions to generate RISC-V opcodes.
+// TODO: Does this already exist somewhere?
+
+static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
+  return (value >> lo) & ((1 << (hi+1-lo)) - 1);
+}
+static uint32_t bit(uint32_t value, unsigned int b) {
+  return (value >> b) & 1;
+}
+
+static uint32_t jal(unsigned int rd, uint32_t imm) {
+  return (bit(imm, 20) << 31) |
+    (bits(imm, 10, 1) << 21) |
+    (bit(imm, 11) << 20) |
+    (bits(imm, 19, 12) << 12) |
+    (rd << 7) |
+    0x6f;
+}
+
 template <typename T>
 unsigned int circular_buffer_t<T>::size() const
 {
@@ -122,6 +141,15 @@ gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
   }
 }
 
+void gdbserver_t::write_debug_ram(unsigned int index, uint32_t value)
+{
+  char *ram = sim->debug_ram() + 4 * index;
+  ram[0] = value & 0xff;
+  ram[1] = (value >> 8) & 0xff;
+  ram[2] = (value >> 16) & 0xff;
+  ram[3] = (value >> 24) & 0xff;
+}
+
 void gdbserver_t::accept()
 {
   client_fd = ::accept(socket_fd, NULL, NULL);
@@ -141,6 +169,7 @@ void gdbserver_t::accept()
 
     // gdb wants the core to be halted when it attaches.
     processor_t *p = sim->get_core(0);
+    write_debug_ram(0, jal(0, (uint32_t) (DEBUG_ROM_START + 4 - DEBUG_RAM_START)));
     p->set_debug_int();
   }
 }
diff --git a/riscv/gdbserver.h b/riscv/gdbserver.h
index 7e7ccbc..b75e990 100644
--- a/riscv/gdbserver.h
+++ b/riscv/gdbserver.h
@@ -115,6 +115,9 @@ private:
   void send_packet(const char* data);
   uint8_t running_checksum;
   void send_running_checksum();
+
+  // Write value to the index'th word in Debug RAM.
+  void write_debug_ram(unsigned int index, uint32_t value);
 };
 
 #endif
diff --git a/riscv/sim.h b/riscv/sim.h
index dad32ef..2e7b214 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -89,6 +89,11 @@ private:
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
 
+  // Return a pointer to Debug RAM in spike address space.
+  char *debug_ram() const {
+      return mem + memsz - DEBUG_SIZE + DEBUG_RAM_START - DEBUG_START;
+  }
+
   friend class htif_isasim_t;
   friend class processor_t;
   friend class mmu_t;