From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 19 May 2019 15:34:50 +0000 (+0100)
Subject: sync ok on simple add
X-Git-Tag: div_pipeline~2011
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=191beb36cf96ea3104b24b30e7ad5bdb99189078;p=soc.git

sync ok on simple add
---

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 016b9104..71a4c680 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -36,16 +36,16 @@ class ComputationUnitNoDelay(Elaboratable):
         # latches be set at the same time.
 
         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
-        m.d.comb += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
-        m.d.comb += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
+        m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
+        m.d.sync += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
 
         # src operand latch (not using go_wr_i)
-        m.d.comb += src_l.s.eq(self.issue_i)
-        m.d.comb += src_l.r.eq(self.go_rd_i)
+        m.d.sync += src_l.s.eq(self.issue_i)
+        m.d.sync += src_l.r.eq(self.go_rd_i)
 
         # dest operand latch (not using issue_i)
-        m.d.comb += req_l.s.eq(self.go_rd_i)
-        m.d.comb += req_l.r.eq(self.go_wr_i)
+        m.d.sync += req_l.s.eq(self.go_rd_i)
+        m.d.sync += req_l.r.eq(self.go_wr_i)
 
         # XXX
         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index b5f37bb9..b7ebf6aa 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -253,8 +253,8 @@ class Scoreboard(Elaboratable):
         go_wr_o = intpick1.go_wr_o
         go_rd_i = intfus.go_rd_i
         go_wr_i = intfus.go_wr_i
-        m.d.sync += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
-        m.d.sync += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
+        m.d.comb += go_rd_i[0:2].eq(go_rd_o[0:2]) # add rd
+        m.d.comb += go_wr_i[0:2].eq(go_wr_o[0:2]) # add wr
 
         # Connect Picker
         #---------
@@ -281,9 +281,9 @@ class Scoreboard(Elaboratable):
         m.d.comb += cu.src2_data_i.eq(int_src2.data_o)
 
         # connect ALU Computation Units
-        m.d.sync += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
-        m.d.sync += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
-        m.d.sync += cu.issue_i[0:2].eq(fn_issue_o[0:2])
+        m.d.comb += cu.go_rd_i[0:2].eq(go_rd_o[0:2])
+        m.d.comb += cu.go_wr_i[0:2].eq(go_wr_o[0:2])
+        m.d.comb += cu.issue_i[0:2].eq(fn_issue_o[0:2])
 
         return m
 
@@ -400,27 +400,27 @@ def scoreboard_sim(dut, alusim):
 
         print ("instr %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
         yield from int_instr(dut, alusim, op, src1, src2, dest)
-        yield from print_reg(dut, [3,4,5])
+        yield from print_reg(dut, [1,2,3])
         while True:
             yield
             issue_o = yield dut.issue_o
             if issue_o:
-                yield from print_reg(dut, [3,4,5])
+                yield from print_reg(dut, [1,2,3])
                 for i in range(len(dut.int_insn_i)):
                     yield dut.int_insn_i[i].eq(0)
                     yield dut.reg_enable_i.eq(0)
                 break
             print ("busy",)
-            yield from print_reg(dut, [3,4,5])
+            yield from print_reg(dut, [1,2,3])
 
     yield
-    yield from print_reg(dut, [3,4,5])
+    yield from print_reg(dut, [1,2,3])
     yield
-    yield from print_reg(dut, [3,4,5])
+    yield from print_reg(dut, [1,2,3])
     yield
-    yield from print_reg(dut, [3,4,5])
+    yield from print_reg(dut, [1,2,3])
     yield
-    yield from print_reg(dut, [3,4,5])
+    yield from print_reg(dut, [1,2,3])
     yield
     yield
     yield