From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Apr 2019 07:29:26 +0000 (+0100)
Subject: quick FIFOtest works!
X-Git-Tag: ls180-24jan2020~1268
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19231bf8cc65cc8259990e3c50049bd2d31c3279;p=ieee754fpu.git

quick FIFOtest works!
---

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index d7aee14d..5e76b2ab 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -199,11 +199,15 @@ class PrevControl:
             return self.s_o_ready # set dynamically by stage
         return self._o_ready      # return this when not under dynamic control
 
-    def _connect_in(self, prev):
+    def _connect_in(self, prev, direct=False):
         """ internal helper function to connect stage to an input source.
             do not use to connect stage-to-stage!
         """
-        return [self.i_valid.eq(prev.i_valid_test),
+        if direct:
+            i_valid = prev.i_valid
+        else:
+            i_valid = prev.i_valid_test
+        return [self.i_valid.eq(i_valid),
                 prev.o_ready.eq(self.o_ready),
                 eq(self.i_data, prev.i_data),
                ]
@@ -257,12 +261,16 @@ class NextControl:
                 eq(nxt.i_data, self.o_data),
                ]
 
-    def _connect_out(self, nxt):
+    def _connect_out(self, nxt, direct=False):
         """ internal helper function to connect stage to an output source.
             do not use to connect stage-to-stage!
         """
+        if direct:
+            i_ready = nxt.i_ready
+        else:
+            i_ready = nxt.i_ready_test
         return [nxt.o_valid.eq(self.o_valid),
-                self.i_ready.eq(nxt.i_ready_test),
+                self.i_ready.eq(i_ready),
                 eq(nxt.o_data, self.o_data),
                ]
 
@@ -934,14 +942,15 @@ class FIFOtest(ControlBase):
         self.m = m = ControlBase._elaborate(self, platform)
 
         fifo = SyncFIFO(self.fwidth, self.fdepth)
+        m.submodules.fifo = fifo
 
         # prev: make the FIFO "look" like a PrevControl...
         fp = PrevControl()
-        fp.i_valid = fifo.writable
-        fp._o_ready = fifo.we
+        fp.i_valid = fifo.we
+        fp._o_ready = fifo.writable
         fp.i_data = fifo.din
         # ... so we can do this!
-        m.d.comb += fp._connect_in(self)
+        m.d.comb += fp._connect_in(self.p, True)
         
         # next: make the FIFO "look" like a NextControl...
         fn = NextControl()
@@ -949,7 +958,7 @@ class FIFOtest(ControlBase):
         fn.i_ready = fifo.re
         fn.o_data = fifo.dout
         # ... so we can do this!
-        m.d.comb += fn._connect_out(self)
+        m.d.comb += fn._connect_out(self.n)
 
         # err... that should be all!
         return m
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 3a15ab6d..fcb1ca31 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -28,6 +28,7 @@ from singlepipe import UnbufferedPipeline2
 from singlepipe import SimpleHandshake
 from singlepipe import PassThroughHandshake
 from singlepipe import PassThroughStage
+from singlepipe import FIFOtest
 
 from random import randint, seed
 
@@ -758,6 +759,16 @@ class ExampleBufPassThruPipe(ControlBase):
         return m
 
 
+######################################################################
+# Test 20
+######################################################################
+
+class FIFOTest16(FIFOtest):
+
+    def __init__(self):
+        FIFOtest.__init__(self, 16, 2)
+
+
 ######################################################################
 # Test 997
 ######################################################################
@@ -1031,6 +1042,18 @@ if __name__ == '__main__':
     with open("test_bufpass19.il", "w") as f:
         f.write(vl)
 
+    print ("test 20")
+    dut = FIFOTest16()
+    data = data_chain1()
+    test = Test5(dut, test_identical_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_fifo20.il", "w") as f:
+        f.write(vl)
+
     print ("test 997")
     dut = ExampleBufPassThruPipe2()
     data = data_chain1()