From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 02:48:16 +0000 (-0700)
Subject: techmap -max_iter to apply to each module individually
X-Git-Tag: working-ls180~1119^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=193eae0c84860c65bd5dd135b7e59c0c11ea76b0;p=yosys.git

techmap -max_iter to apply to each module individually
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index b271c8781..a6c1214a7 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -943,7 +943,8 @@ struct TechmapPass : public Pass {
 		log("        instead of inlining them.\n");
 		log("\n");
 		log("    -max_iter <number>\n");
-		log("        only run the specified number of iterations.\n");
+		log("        only run the specified number of iterations for each module.\n");
+		log("        default: unlimited\n");
 		log("\n");
 		log("    -recursive\n");
 		log("        instead of the iterative breadth-first algorithm use a recursive\n");
@@ -1157,15 +1158,16 @@ struct TechmapPass : public Pass {
 			RTLIL::Module *module = *worker.module_queue.begin();
 			worker.module_queue.erase(module);
 
+			int module_max_iter = max_iter;
 			bool did_something = true;
 			std::set<RTLIL::Cell*> handled_cells;
 			while (did_something) {
 				did_something = false;
-					if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
-						did_something = true;
+				if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
+					did_something = true;
 				if (did_something)
 					module->check();
-				if (max_iter > 0 && --max_iter == 0)
+				if (module_max_iter > 0 && --module_max_iter == 0)
 					break;
 			}
 		}