From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Fri, 10 Jul 2020 15:46:06 +0000 (+0200)
Subject: Improve simulation output: add names to submodules
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1948ded572bc3def97ef68dfe08771c242143ca8;p=gram.git

Improve simulation output: add names to submodules
---

diff --git a/gram/core/__init__.py b/gram/core/__init__.py
index 950a2de..da2b78a 100644
--- a/gram/core/__init__.py
+++ b/gram/core/__init__.py
@@ -51,14 +51,14 @@ class gramCore(Peripheral, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        m.submodules += self._bridge
+        m.submodules.bridge = self._bridge
 
-        m.submodules += self.dfii
+        m.submodules.dfii = self.dfii
         m.d.comb += self.dfii.master.connect(self._phy.dfi)
 
         m.submodules.controller = self.controller
         m.d.comb += self.controller.dfi.connect(self.dfii.slave)
 
-        m.submodules += self.crossbar
+        m.submodules.crossbar = self.crossbar
 
         return m
diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py
index 84c32b8..9730eca 100644
--- a/gram/core/multiplexer.py
+++ b/gram/core/multiplexer.py
@@ -71,8 +71,7 @@ class _CommandChooser(Elaboratable):
             write = request.is_write == self.want_writes
             m.d.comb += valids[i].eq(request.valid & (command | (read & write)))
 
-        arbiter = RoundRobin(n)
-        m.submodules += arbiter
+        m.submodules.arbiter = arbiter = RoundRobin(n)
         choices = Array(valids[i] for i in range(n))
         m.d.comb += [
             arbiter.request.eq(valids),
@@ -304,8 +303,7 @@ class Multiplexer(Elaboratable):
                                         log2_int(len(bank_machines))))
         # nop must be 1st
         commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd]
-        steerer = _Steerer(commands, dfi)
-        m.submodules += steerer
+        m.submodules.steerer = steerer = _Steerer(commands, dfi)
 
         # tRRD timing (Row to Row delay) -----------------------------------------------------------
         m.submodules.trrdcon = trrdcon = tXXDController(settings.timing.tRRD)
diff --git a/gram/core/refresher.py b/gram/core/refresher.py
index 9101c8e..7c68fec 100644
--- a/gram/core/refresher.py
+++ b/gram/core/refresher.py
@@ -44,7 +44,7 @@ class RefreshExecuter(Elaboratable):
         trp = self._trp
         trfc = self._trfc
 
-        tl = Timeline([
+        m.submodules.timeline = tl = Timeline([
             # Precharge All
             (0, [
                 self.a.eq(2**10),
@@ -71,7 +71,6 @@ class RefreshExecuter(Elaboratable):
                 self.done.eq(1),
             ]),
         ])
-        m.submodules += tl
         m.d.comb += tl.trigger.eq(self.start)
 
         return m
@@ -104,8 +103,7 @@ class RefreshSequencer(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        executer = RefreshExecuter(self._abits, self._babits, self._trp, self._trfc)
-        m.submodules += executer
+        m.submodules.executer = executer = RefreshExecuter(self._abits, self._babits, self._trp, self._trfc)
         m.d.comb += [
             self.a.eq(executer.a),
             self.ba.eq(executer.ba),
@@ -257,7 +255,7 @@ class ZQCSExecuter(Elaboratable):
         trp = self._trp
         tzqcs = self._tzqcs
 
-        tl = Timeline([
+        m.submodules.timeline = tl = Timeline([
             # Precharge All
             (0, [
                 self.a.eq(2**10),
@@ -286,7 +284,6 @@ class ZQCSExecuter(Elaboratable):
                 self.done.eq(1)
             ]),
         ])
-        m.submodules += tl
         m.d.comb += tl.trigger.eq(self.start)
 
         return m