From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 01:38:40 +0000 (+0100)
Subject: move RS to operand a (1st position) for MTMSR and MTSPR
X-Git-Tag: convert-csv-opcode-to-binary~2549
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1970241a6db97d4ace1e053e72f2a3d9462e98b2;p=libreriscv.git

move RS to operand a (1st position) for MTMSR and MTSPR
---

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 2452519cc..5fc9a121c 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -112,8 +112,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,modsd,X
 0b1100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,1,NONE,0,0,modsw,X
 0b0010010000,CR,OP_MTCRF,RS,NONE,NONE,NONE,WHOLE_REG,WHOLE_REG,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtcrf/mtocrf,XFX
-0b0010110010,ALU,OP_MTMSRD,NONE,NONE,RS,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd # ignore top bits and d,X
-0b0111010011,ALU,OP_MTSPR,NONE,NONE,RS,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
+0b0010110010,ALU,OP_MTMSRD,RS,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd # ignore top bits and d,X
+0b0111010011,ALU,OP_MTSPR,RS,NONE,NONE,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
 0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
 0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO
 0b0001001011,MUL,OP_MUL_H32,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,1,RC,0,0,mulhw,XO