From: Christian Bruel Date: Mon, 16 Nov 2015 08:46:42 +0000 (+0100) Subject: re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not available) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19708abc4b44fd91987f98a8af67a1720a034e32;p=gcc.git re PR target/65837 ([arm-linux-gnueabihf] lto1 target specific builtin not available) 2015-11-16 Christian Bruel PR target/65837 * config/arm/arm.c (arm_fpu_desc): Remove. (all_fpus): Make global. (arm_option_override): Use FPU TARGET accessors. (arm_declare_function_name): Likewise. * config/arm/arm.h (TARGET_VFP, TARGET_VFPD32, TARGET_VFP5) (TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE, TARGET_NEON_FP16) (TARGET_FP16, TARGET_FMA, TARGET_FPU_ARMV8, TARGET_CRYPTO) (TARGET_NEON): Likewise. (all_fpus): Declare extern. (TARGET_FPU_NAME, TARGET_FPU_MODEL, TARGET_FPU_REV) (TARGET_FPU_REGS, TARGET_FPU_FEATURES): Define all_fpus accessors. From-SVN: r230404 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 09a165d4c22..3d8679b4635 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-11-16 Christian Bruel + + PR target/65837 + * config/arm/arm.c (arm_fpu_desc): Remove. + (all_fpus): Make global. + (arm_option_override): Use FPU TARGET accessors. + (arm_declare_function_name): Likewise. + * config/arm/arm.h (TARGET_VFP, TARGET_VFPD32, TARGET_VFP5) + (TARGET_VFP_SINGLE, TARGET_VFP_DOUBLE, TARGET_NEON_FP16) + (TARGET_FP16, TARGET_FMA, TARGET_FPU_ARMV8, TARGET_CRYPTO) + (TARGET_NEON): Likewise. + (all_fpus): Declare extern. + (TARGET_FPU_NAME, TARGET_FPU_MODEL, TARGET_FPU_REV) + (TARGET_FPU_REGS, TARGET_FPU_FEATURES): Define all_fpus accessors. + 2015-11-15 Trevor Saunders PR middle-end/68366 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index e31be67328d..10c4348d7f3 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -759,9 +759,6 @@ const struct tune_params *current_tune; /* Which floating point hardware to schedule for. */ int arm_fpu_attr; -/* Which floating popint hardware to use. */ -const struct arm_fpu_desc *arm_fpu_desc; - /* Used for Thumb call_via trampolines. */ rtx thumb_call_via_label[14]; static int thumb_call_reg_needed; @@ -2224,7 +2221,7 @@ char arm_arch_name[] = "__ARM_ARCH_0UNK__"; /* Available values for -mfpu=. */ -static const struct arm_fpu_desc all_fpus[] = +const struct arm_fpu_desc all_fpus[] = { #define ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) \ { NAME, MODEL, REV, VFP_REGS, FEATURES }, @@ -2232,7 +2229,6 @@ static const struct arm_fpu_desc all_fpus[] = #undef ARM_FPU }; - /* Supported TLS relocations. */ enum tls_reloc { @@ -3139,17 +3135,13 @@ arm_option_override (void) gcc_assert (ok); } - arm_fpu_desc = &all_fpus[arm_fpu_index]; - - switch (arm_fpu_desc->model) - { - case ARM_FP_MODEL_VFP: - arm_fpu_attr = FPU_VFP; - break; - - default: - gcc_unreachable(); - } + /* If soft-float is specified then don't use FPU. */ + if (TARGET_SOFT_FLOAT) + arm_fpu_attr = FPU_NONE; + else if (TARGET_VFP) + arm_fpu_attr = FPU_VFP; + else + gcc_unreachable(); if (TARGET_AAPCS_BASED) { @@ -3164,10 +3156,6 @@ arm_option_override (void) if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE) sorry ("__fp16 and no ldrh"); - /* If soft-float is specified then don't use FPU. */ - if (TARGET_SOFT_FLOAT) - arm_fpu_attr = FPU_NONE; - if (TARGET_AAPCS_BASED) { if (arm_abi == ARM_ABI_IWMMXT) @@ -29974,8 +29962,8 @@ arm_declare_function_name (FILE *stream, const char *name, tree decl) else fprintf (stream, "\t.arm\n"); - asm_fprintf (asm_out_file, "\t.fpu %s\n", TARGET_SOFT_FLOAT - ? "softvfp" : arm_fpu_desc->name); + asm_fprintf (asm_out_file, "\t.fpu %s\n", + TARGET_SOFT_FLOAT ? "softvfp" : TARGET_FPU_NAME); if (TARGET_POKE_FUNCTION_NAME) arm_poke_function_name (stream, (const char *) name); diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 313fed5b450..6ed8ad3823e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -138,7 +138,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) -#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) +#define TARGET_VFP (TARGET_FPU_MODEL == ARM_FP_MODEL_VFP) #define TARGET_IWMMXT (arm_arch_iwmmxt) #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) @@ -176,39 +176,38 @@ extern void (*arm_lang_output_object_attributes_hook)(void); to be more careful with TARGET_NEON as noted below. */ /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ -#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) +#define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32) /* FPU supports VFPv3 instructions. */ -#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) +#define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3) /* FPU supports FPv5 instructions. */ -#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) +#define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5) /* FPU only supports VFP single-precision instructions. */ -#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) +#define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE) /* FPU supports VFP double-precision instructions. */ -#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) +#define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE) /* FPU supports half-precision floating-point with NEON element load/store. */ #define TARGET_NEON_FP16 \ (TARGET_VFP \ - && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON | FPU_FL_FP16)) + && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON | FPU_FL_FP16)) /* FPU supports VFP half-precision floating-point. */ #define TARGET_FP16 \ - (TARGET_VFP && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_FP16)) + (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16)) /* FPU supports fused-multiply-add operations. */ -#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) +#define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4) /* FPU is ARMv8 compatible. */ -#define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) +#define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8) /* FPU supports Crypto extensions. */ #define TARGET_CRYPTO \ - (TARGET_VFP && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_CRYPTO)) - + (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO)) /* FPU supports Neon instructions. The setting of this macro gets revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT @@ -216,7 +215,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); available. */ #define TARGET_NEON \ (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \ - && ARM_FPU_FSET_HAS (arm_fpu_desc->features, FPU_FL_NEON)) + && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)) /* Q-bit is present. */ #define TARGET_ARM_QBIT \ @@ -346,7 +345,15 @@ extern const struct arm_fpu_desc int rev; enum vfp_reg_type regs; arm_fpu_feature_set features; -} *arm_fpu_desc; +} all_fpus[]; + +/* Accessors. */ + +#define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name) +#define TARGET_FPU_MODEL (all_fpus[arm_fpu_index].model) +#define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev) +#define TARGET_FPU_REGS (all_fpus[arm_fpu_index].regs) +#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features) /* Which floating point hardware to schedule for. */ extern int arm_fpu_attr;