From: lkcl <lkcl@web>
Date: Wed, 22 Nov 2023 14:52:40 +0000 (+0000)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=197ce5c79a4fa992ef3cf0e1b11a4ffac29f16b6;p=libreriscv.git

---

diff --git a/nlnet_2023_svp64_riscv.mdwn b/nlnet_2023_svp64_riscv.mdwn
index 1298c3cc8..f385defe9 100644
--- a/nlnet_2023_svp64_riscv.mdwn
+++ b/nlnet_2023_svp64_riscv.mdwn
@@ -55,6 +55,8 @@ EUR 100,000.
   modernising the work already done four years ago under
   NLnet Grant 2019-10-012 <https://libre-soc.org/nlnet_2018/>
 * Implementing Simple-V in the Libre-SOC Simulator, ISACaller.
+* Assembler and disassembler of RISC-V instructions and also
+  SVP64 in the Libre-SOC infrastructure.
 * Upgrading sv-spike which was completed four years ago with
   an early prototype Simple-V Specification
   <https://git.libre-soc.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv>