From: Florent Kermarrec Date: Thu, 2 Jan 2020 08:41:47 +0000 (+0100) Subject: soc/integration/soc_core/SoCController: specify initial reset value of scratch regist... X-Git-Tag: 24jan2021_ls180~777 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=197edad34e22a70d966b4f95c183294d8eb906cd;p=litex.git soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 9e99f56d..6c564e22 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -45,8 +45,8 @@ class SoCController(Module, AutoCSR): Write a ``1`` to this register to reset the SoC.""") self._scratch = CSRStorage(32, reset=0x12345678, description=""" Use this register as a scratch space to verify that software read/write accesses - to the Wishbone/CSR bus are working correctly. The initial reset value can be used - to verify endianness.""") + to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578 + can be used to verify endianness.""") self._bus_errors = CSRStatus(32, description=""" Total number of Wishbone bus errors (timeouts) since last reset.""")