From: whitequark <cz@m-labs.hk>
Date: Fri, 21 Dec 2018 01:51:18 +0000 (+0000)
Subject: back.rtlil: explicitly pad constants with zeroes.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=198050c59bf07c3b0369325bcdcb7a4b7cc9b84d;p=nmigen.git

back.rtlil: explicitly pad constants with zeroes.

I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 433dd20..0b61268 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -353,7 +353,7 @@ class _RHSValueCompiler(_ValueCompiler):
         if isinstance(value.value, str):
             return "{}'{}".format(value.nbits, value.value)
         else:
-            return "{}'{:b}".format(value.nbits, value.value)
+            return "{}'{:0{}b}".format(value.nbits, value.value, value.nbits)
 
     def on_Signal(self, value):
         wire_curr, wire_next = self.s.resolve(value)