From: Gabe Black <gabeblack@google.com>
Date: Wed, 19 Aug 2020 09:11:54 +0000 (-0700)
Subject: arch: Eliminate an unused pair of constants from isa_traits.hh.
X-Git-Tag: v20.1.0.0~265
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1981c3110d3433bf44ffbec64a77cf703540fddf;p=gem5.git

arch: Eliminate an unused pair of constants from isa_traits.hh.

The one questionable use of CurThreadInfoImplemented (always false) and
CurThreadInfoReg (always -1) has been eliminated, making these constants
unnecessary.

Change-Id: Ibfe4f7be7ce5aaf9c5e896146e1b05b3ac752305
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32922
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index c9b6eb997..0ce38bcc9 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -95,9 +95,6 @@ namespace ArmISA
     // Memory accesses cannot be unaligned
     const bool HasUnalignedMemAcc = true;
 
-    const bool CurThreadInfoImplemented = false;
-    const int CurThreadInfoReg = -1;
-
     enum InterruptTypes
     {
         INT_RST,
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5d20f7cb6..9b44d8649 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -138,9 +138,6 @@ const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
 const bool HasUnalignedMemAcc = true;
 
-const bool CurThreadInfoImplemented = false;
-const int CurThreadInfoReg = -1;
-
 } // namespace MipsISA
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 25499ffe9..89bfa6bb5 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -57,9 +57,6 @@ const int MachineBytes = 4;
 // Memory accesses can be unaligned
 const bool HasUnalignedMemAcc = true;
 
-const bool CurThreadInfoImplemented = false;
-const int CurThreadInfoReg = -1;
-
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_TRAITS_HH__
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 18cf48513..8ba2e0cdc 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@ const Addr PageBytes = ULL(1) << PageShift;
 // Memory accesses can be unaligned (at least for double-word memory accesses)
 const bool HasUnalignedMemAcc = true;
 
-const bool CurThreadInfoImplemented = false;
-const int CurThreadInfoReg = -1;
-
 }
 
 #endif //__ARCH_RISCV_ISA_TRAITS_HH__
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 3cd621607..798910762 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -47,9 +47,6 @@ StaticInstPtr decodeInst(ExtMachInst);
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 
-const bool CurThreadInfoImplemented = false;
-const int CurThreadInfoReg = -1;
-
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 7f55145c3..98a2dc843 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -52,9 +52,6 @@ namespace X86ISA
 
     // Memory accesses can be unaligned
     const bool HasUnalignedMemAcc = true;
-
-    const bool CurThreadInfoImplemented = false;
-    const int CurThreadInfoReg = -1;
 }
 
 #endif // __ARCH_X86_ISATRAITS_HH__