From: lkcl <lkcl@web>
Date: Mon, 29 May 2023 23:51:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19973c2bb3a343e70c4699f2388251afd36fd542;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index eca3eeaca..3c94ca182 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -52,7 +52,7 @@ actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
 Vector instructions on the SFFS Subset and closer to 10 million 64-bit
 True-Scalable Vector instructions if introduced on VSX.  SVP64, the
 instruction format used by Simple-V, is therefore best viewed as an
-orthogonal RISC-paradigm "Prefixing" subsystem instead.
+orthogonal RISC-paradigm "Loop Prefixing" subsystem instead.
 
 [^bib_ldir]:  [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
 [^bib_cpir]:  [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)