From: Dmitry Selyutin Date: Fri, 9 Sep 2022 13:55:56 +0000 (+0300) Subject: minor_30: fix rldcl/rldcr forms X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19992d7ca28452d3c167bf50f5e8d20f5aacd029;p=openpower-isa.git minor_30: fix rldcl/rldcr forms --- diff --git a/openpower/isatables/minor_30.csv b/openpower/isatables/minor_30.csv index 9af910d2..3a598373 100644 --- a/openpower/isatables/minor_30.csv +++ b/openpower/isatables/minor_30.csv @@ -5,5 +5,5 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 000-,SHIFT_ROT,OP_RLCL,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicl,MDS, 001-,SHIFT_ROT,OP_RLCR,NONE,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldicr,MD, 011-,SHIFT_ROT,OP_RLC,RA,CONST_SH,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldimi,MD, -1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcl,MD, -1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcr,MD, +1000,SHIFT_ROT,OP_RLCL,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcl,MDS, +1001,SHIFT_ROT,OP_RLCR,NONE,RB,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,rldcr,MDS,