From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 7 Jun 2018 09:48:15 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5255
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19b39b9e4bc07328bed90fc1e6cb3ba94ec7bac1;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 43b49ff84..1b99f95cd 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -681,7 +681,7 @@ loop:
 	     (scalar ops are just vectors of length 1)\vspace{4pt}
    \item Tightly coupled with the core (instruction issue)\\
          could be disabled through MISA switch\vspace{4pt}
-   \item An extra pipeline phase is pretty much essential\\
+   \item An extra pipeline phase almost certainly essential\\
          for fast low-latency implementations\vspace{4pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
          it is however an optimisation (and could be skipped).\vspace{4pt}