From: YRabbit <rabbit@yrabbit.cyou>
Date: Mon, 14 Mar 2022 21:41:30 +0000 (+1000)
Subject: gowin: add support for Double Data Rate primitives
X-Git-Tag: yosys-0.16~42
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19b7633aca6335bfdf79ab1fd71f99060f6e04ca;p=yosys.git

gowin: add support for Double Data Rate primitives

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index b07ee6924..64b76139c 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -590,6 +590,31 @@ module TLVDS_OBUF (I, O, OB);
   assign OB = ~I;
 endmodule
 
+(* blackbox *)
+module ODDR(D0, D1, TX, CLK, Q0, Q1);
+	input D0;
+	input D1;
+	input TX;
+	input CLK;
+	output Q0;
+	output Q1;
+	parameter TXCLK_POL = 0;
+	parameter INIT = 0;
+endmodule
+
+(* blackbox *)
+module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
+	input D0;
+	input D1;
+	input CLEAR;
+	input TX;
+	input CLK;
+	output Q0;
+	output Q1;
+	parameter TXCLK_POL = 0;
+	parameter INIT = 0;
+endmodule
+
 module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule