From: Steve Reinhardt <stever@gmail.com>
Date: Sat, 15 Mar 2008 12:03:55 +0000 (-0700)
Subject: Fix subtle cache bug where read could return stale data
X-Git-Tag: copyright_update~20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19c367fa8fa0c330676c1b7aacb532b8871164cf;p=gem5.git

Fix subtle cache bug where read could return stale data
if a prior write miss arrived while an even earlier
read miss was still outstanding.

--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
---

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e546e2a9a..5aecea7d5 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -825,6 +825,10 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
     }
 
     if (mshr->promoteDeferredTargets()) {
+        assert(mshr->needsExclusive() && !blk->isWritable());
+        // avoid later read getting stale data while write miss is
+        // outstanding.. see comment in timingAccess()
+        blk->status &= ~BlkReadable;
         MSHRQueue *mq = mshr->queue;
         mq->markPending(mshr);
         requestMemSideBus((RequestCause)mq->index, pkt->finishTime);