From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 19 May 2020 20:22:38 +0000 (+0100)
Subject: update comments
X-Git-Tag: div_pipeline~1067
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19c9b69f9dcbde7d5071bdb05c8eb5f671db5179;p=soc.git

update comments
---

diff --git a/libreriscv b/libreriscv
index 6ce15b77..3e665eb7 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 6ce15b77d086f4f2d0b945b032fbaa2096f2ef6f
+Subproject commit 3e665eb7607d37b92567a445e795c4d7b6e00fc9
diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 751a1835..581040c4 100644
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -26,10 +26,10 @@ class TrapInputData(IntegerData):
 class TrapOutputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)
-        self.nia = Signal(64, reset_less=True) # RA
-        self.msr = Signal(64, reset_less=True) # RB/immediate
-        self.srr0 = Signal(64, reset_less=True) # RB/immediate
-        self.srr1 = Signal(64, reset_less=True) # RB/immediate
+        self.nia = Signal(64, reset_less=True) # NIA (Next PC)
+        self.msr = Signal(64, reset_less=True) # MSR
+        self.srr0 = Signal(64, reset_less=True) # SRR0 SPR
+        self.srr1 = Signal(64, reset_less=True) # SRR1 SPR
         self.should_trap = Signal(reset_less=True)
 
     def __iter__(self):