From: Jacob Lifshay <programmerjake@gmail.com>
Date: Tue, 4 Apr 2023 05:04:48 +0000 (-0700)
Subject: sync table reformatting from ls006 -> int_fp_mv
X-Git-Tag: opf_rfc_ls012_v1~131
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19d678675643cb293112a0770a551074076b7a3f;p=libreriscv.git

sync table reformatting from ls006 -> int_fp_mv
---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 5a8d198a9..221682d0e 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -473,12 +473,16 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
-|----------------------|----------------------|------|----------------------|----------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2`  |
-| `fcvtfgw. FRT, RB`   | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg. FRT, RB, 2` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3`  |
-| `fcvtfguw. FRT, RB`  | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg. FRT, RB, 3` |
+| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|
+| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0`  |
+| `fcvtfgw. FRT, RB`   | `fcvtfg. FRT, RB, 0` |
+| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1`  |
+| `fcvtfguw. FRT, RB`  | `fcvtfg. FRT, RB, 1` |
+| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgd. FRT, RB`   | `fcvtfg. FRT, RB, 2` |
+| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3`  |
+| `fcvtfgud. FRT, RB`  | `fcvtfg. FRT, RB, 3` |
 
 ## Floating Convert From Integer In GPR Single
 
@@ -534,12 +538,16 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction     |&nbsp;| Assembly Alias       | Full Instruction     |
-|----------------------|----------------------|------|----------------------|----------------------|
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0`  |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2`  |
-| `fcvtfgws. FRT, RB`  | `fcvtfg. FRT, RB, 0` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg. FRT, RB, 2` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1`  |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3`  |
-| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
+| Assembly Alias       | Full Instruction     |
+|----------------------|----------------------|
+| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0`  |
+| `fcvtfgws. FRT, RB`  | `fcvtfg. FRT, RB, 0` |
+| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1`  |
+| `fcvtfguws. FRT, RB` | `fcvtfg. FRT, RB, 1` |
+| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2`  |
+| `fcvtfgds. FRT, RB`  | `fcvtfg. FRT, RB, 2` |
+| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3`  |
+| `fcvtfguds. FRT, RB` | `fcvtfg. FRT, RB, 3` |
 
 ## Floating-point to Integer Conversion Overview
 
@@ -810,16 +818,24 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-| Assembly Alias            | Full Instruction           | Assembly Alias            | Full Instruction           |
-|---------------------------|----------------------------|---------------------------|----------------------------|
-| `fcvttgw RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 0`   | `fcvttgd RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 2`   |
-| `fcvttgw. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 0`  | `fcvttgd. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 2`  |
-| `fcvttgwo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 0`  | `fcvttgdo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 2`  |
-| `fcvttgwo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 0` | `fcvttgdo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 2` |
-| `fcvttguw RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 1`   | `fcvttgud RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 3`   |
-| `fcvttguw. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 1`  | `fcvttgud. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 3`  |
-| `fcvttguwo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 1`  | `fcvttgudo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 3`  |
-| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` | `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
+| Assembly Alias            | Full Instruction           |
+|---------------------------|----------------------------|
+| `fcvttgw RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 0`   |
+| `fcvttgw. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 0`  |
+| `fcvttgwo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 0`  |
+| `fcvttgwo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 0` |
+| `fcvttguw RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 1`   |
+| `fcvttguw. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 1`  |
+| `fcvttguwo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 1`  |
+| `fcvttguwo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 1` |
+| `fcvttgd RT, FRB, CVM`    | `fcvttg RT, FRB, CVM, 2`   |
+| `fcvttgd. RT, FRB, CVM`   | `fcvttg. RT, FRB, CVM, 2`  |
+| `fcvttgdo RT, FRB, CVM`   | `fcvttgo RT, FRB, CVM, 2`  |
+| `fcvttgdo. RT, FRB, CVM`  | `fcvttgo. RT, FRB, CVM, 2` |
+| `fcvttgud RT, FRB, CVM`   | `fcvttg RT, FRB, CVM, 3`   |
+| `fcvttgud. RT, FRB, CVM`  | `fcvttg. RT, FRB, CVM, 3`  |
+| `fcvttgudo RT, FRB, CVM`  | `fcvttgo RT, FRB, CVM, 3`  |
+| `fcvttgudo. RT, FRB, CVM` | `fcvttgo. RT, FRB, CVM, 3` |
 
 ## Floating Convert Single To Integer In GPR
 
@@ -958,13 +974,21 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-| Assembly Alias             | Full Instruction            | Assembly Alias             | Full Instruction            |
-|----------------------------|-----------------------------|----------------------------|-----------------------------|
-| `fcvtstgw RT, FRB, CVM`    | `fcvtstg RT, FRB, CVM, 0`   | `fcvtstgd RT, FRB, CVM`    | `fcvtstg RT, FRB, CVM, 2`   |
-| `fcvtstgw. RT, FRB, CVM`   | `fcvtstg. RT, FRB, CVM, 0`  | `fcvtstgd. RT, FRB, CVM`   | `fcvtstg. RT, FRB, CVM, 2`  |
-| `fcvtstgwo RT, FRB, CVM`   | `fcvtstgo RT, FRB, CVM, 0`  | `fcvtstgdo RT, FRB, CVM`   | `fcvtstgo RT, FRB, CVM, 2`  |
-| `fcvtstgwo. RT, FRB, CVM`  | `fcvtstgo. RT, FRB, CVM, 0` | `fcvtstgdo. RT, FRB, CVM`  | `fcvtstgo. RT, FRB, CVM, 2` |
-| `fcvtstguw RT, FRB, CVM`   | `fcvtstg RT, FRB, CVM, 1`   | `fcvtstgud RT, FRB, CVM`   | `fcvtstg RT, FRB, CVM, 3`   |
-| `fcvtstguw. RT, FRB, CVM`  | `fcvtstg. RT, FRB, CVM, 1`  | `fcvtstgud. RT, FRB, CVM`  | `fcvtstg. RT, FRB, CVM, 3`  |
-| `fcvtstguwo RT, FRB, CVM`  | `fcvtstgo RT, FRB, CVM, 1`  | `fcvtstgudo RT, FRB, CVM`  | `fcvtstgo RT, FRB, CVM, 3`  |
-| `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` | `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` |
+| Assembly Alias             | Full Instruction            |
+|----------------------------|-----------------------------|
+| `fcvtstgw RT, FRB, CVM`    | `fcvtstg RT, FRB, CVM, 0`   |
+| `fcvtstgw. RT, FRB, CVM`   | `fcvtstg. RT, FRB, CVM, 0`  |
+| `fcvtstgwo RT, FRB, CVM`   | `fcvtstgo RT, FRB, CVM, 0`  |
+| `fcvtstgwo. RT, FRB, CVM`  | `fcvtstgo. RT, FRB, CVM, 0` |
+| `fcvtstguw RT, FRB, CVM`   | `fcvtstg RT, FRB, CVM, 1`   |
+| `fcvtstguw. RT, FRB, CVM`  | `fcvtstg. RT, FRB, CVM, 1`  |
+| `fcvtstguwo RT, FRB, CVM`  | `fcvtstgo RT, FRB, CVM, 1`  |
+| `fcvtstguwo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 1` |
+| `fcvtstgd RT, FRB, CVM`    | `fcvtstg RT, FRB, CVM, 2`   |
+| `fcvtstgd. RT, FRB, CVM`   | `fcvtstg. RT, FRB, CVM, 2`  |
+| `fcvtstgdo RT, FRB, CVM`   | `fcvtstgo RT, FRB, CVM, 2`  |
+| `fcvtstgdo. RT, FRB, CVM`  | `fcvtstgo. RT, FRB, CVM, 2` |
+| `fcvtstgud RT, FRB, CVM`   | `fcvtstg RT, FRB, CVM, 3`   |
+| `fcvtstgud. RT, FRB, CVM`  | `fcvtstg. RT, FRB, CVM, 3`  |
+| `fcvtstgudo RT, FRB, CVM`  | `fcvtstgo RT, FRB, CVM, 3`  |
+| `fcvtstgudo. RT, FRB, CVM` | `fcvtstgo. RT, FRB, CVM, 3` |