From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Jul 2021 09:59:28 +0000 (+0100)
Subject: comments
X-Git-Tag: xlen-bcd~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=19ea1348084ca0847474f439cc720fd6908c1bac;p=openpower-isa.git

comments
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index 404f7497..159da8c9 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -1,5 +1,4 @@
-<!-- This defines instructions described in PowerISA Version 3.0 B Book 1 -->
-
+<!-- This defines Draft SVP64 instructions to augment PowerISA Version 3.0 -->
 <!-- These are not described in book 1 -->
 
 # setvl
diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index f6d5da7f..df291662 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -315,15 +315,14 @@ class DCTTestCase(FHDLTestCase):
                 self.assertTrue(err < 1e-6)
 
     def test_sv_remap_fpmadds_dct_8(self):
-        """>>> lst = ["svshape 8, 1, 1, 3, 0",
-                     "svremap 27, 1, 0, 2, 0, 1, 0",
-                        "sv.fdmadds 0.v, 0.v, 0.v, 8.v"
-                         "sv.fadds 0.v, 0.v, 0.v"
+        """>>> lst = ["svremap 27, 1, 0, 2, 0, 1, 1",
+                      "svshape 8, 1, 1, 2, 0",
+                      "sv.fdmadds 0.v, 0.v, 0.v, 8.v"
+                      "svshape 8, 1, 1, 3, 0",
+                      "sv.fadds 0.v, 0.v, 0.v"
                      ]
-            runs a full in-place 8-long O(N log2 N) outer butterfly schedule
-            for DCT, does the iterative overlapped ADDs
-
-            SVP64 "REMAP" in Butterfly Mode.
+            runs a full in-place 8-long O(N log2 N) DCT, both
+            inner and outer butterfly "REMAP" schedules.
         """
         lst = SVP64Asm( ["svremap 27, 1, 0, 2, 0, 1, 1",
                          "svshape 8, 1, 1, 2, 0",