From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Jan 2022 16:31:39 +0000 (+0000)
Subject: use microwatt-specific PLRU due to bug in nmutil version
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a10bec46c29e4da101ecb06622d8c19d45681cc;p=soc.git

use microwatt-specific PLRU due to bug in nmutil version
(needs investigating)
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index b9e467bb..6d2d3cf2 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -51,8 +51,8 @@ from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS,
                                 WBIOMasterOut, WBIOSlaveOut)
 
 from soc.experiment.cache_ram import CacheRam
-#from soc.experiment.plru import PLRU
-from nmutil.plru import PLRU, PLRUs
+from soc.experiment.plru import PLRU, PLRUs
+#from nmutil.plru import PLRU, PLRUs
 
 # for test
 from soc.bus.sram import SRAM