From: Gabe Black Date: Tue, 10 Mar 2020 00:11:22 +0000 (-0700) Subject: arch,base,cpu,dev,kern,mem,sim: Drop FS from FSTranslatingPortProxy. X-Git-Tag: v20.0.0.0~306 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a1b84322ba78c0705a14a62d0054d38f4b66364;p=gem5.git arch,base,cpu,dev,kern,mem,sim: Drop FS from FSTranslatingPortProxy. This translating proxy can be used in FS, or in SE with a failure handing case in place. Change-Id: I2e6421f52529fa833e42f8d3e64d4341c282634f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26551 Tested-by: kokoro Reviewed-by: Matthew Poremba Maintainer: Gabe Black --- diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 516565eb5..9aed27b7c 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -32,8 +32,8 @@ #include "arch/arm/utility.hh" #include "iris/detail/IrisCppAdapter.h" #include "iris/detail/IrisObjects.h" -#include "mem/fs_translating_port_proxy.hh" #include "mem/se_translating_port_proxy.hh" +#include "mem/translating_port_proxy.hh" namespace Iris { @@ -407,7 +407,7 @@ ThreadContext::initMemProxies(::ThreadContext *tc) assert(!physProxy && !virtProxy); physProxy.reset(new PortProxy(_cpu->getSendFunctional(), _cpu->cacheLineSize())); - virtProxy.reset(new FSTranslatingPortProxy(tc)); + virtProxy.reset(new TranslatingPortProxy(tc)); } else { assert(!virtProxy); virtProxy.reset(new SETranslatingPortProxy(this, diff --git a/src/arch/arm/freebsd/fs_workload.cc b/src/arch/arm/freebsd/fs_workload.cc index 33e012642..dbadb4b2a 100644 --- a/src/arch/arm/freebsd/fs_workload.cc +++ b/src/arch/arm/freebsd/fs_workload.cc @@ -43,7 +43,6 @@ #include "cpu/thread_context.hh" #include "debug/Loader.hh" #include "kern/freebsd/events.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/physical.hh" #include "sim/stat_control.hh" diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc index 9390a464d..c21ce09f7 100644 --- a/src/arch/arm/linux/fs_workload.cc +++ b/src/arch/arm/linux/fs_workload.cc @@ -55,7 +55,6 @@ #include "kern/linux/events.hh" #include "kern/linux/helpers.hh" #include "kern/system_events.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/physical.hh" #include "sim/stat_control.hh" diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc index 460452427..b5a9976cf 100644 --- a/src/arch/arm/stacktrace.cc +++ b/src/arch/arm/stacktrace.cc @@ -35,7 +35,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/system.hh" namespace ArmISA diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index 9053a5c7d..97c3c5f3c 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -49,7 +49,6 @@ #include "cpu/thread_context.hh" #include "dev/arm/fvp_base_pwr_ctrl.hh" #include "dev/arm/gic_v2.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/physical.hh" using namespace std; diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index a5fc32dbb..96678b07b 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -48,8 +48,8 @@ #include "config/the_isa.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/packet.hh" +#include "mem/port_proxy.hh" #include "sim/core.hh" #include "sim/faults.hh" #include "sim/sim_exit.hh" diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 393f141b0..7c70def08 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -46,7 +46,7 @@ #include "cpu/base.hh" #include "cpu/checker/cpu.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/full_system.hh" namespace ArmISA diff --git a/src/arch/mips/stacktrace.cc b/src/arch/mips/stacktrace.cc index 651719a02..ec5597c55 100644 --- a/src/arch/mips/stacktrace.cc +++ b/src/arch/mips/stacktrace.cc @@ -35,7 +35,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/system.hh" using namespace MipsISA; diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc index b42635fc4..7e797b57f 100644 --- a/src/arch/mips/utility.cc +++ b/src/arch/mips/utility.cc @@ -36,7 +36,6 @@ #include "base/logging.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" #include "sim/serialize.hh" using namespace MipsISA; diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc index ac442cad5..21fbf939d 100644 --- a/src/arch/sparc/utility.cc +++ b/src/arch/sparc/utility.cc @@ -29,7 +29,7 @@ #include "arch/sparc/utility.hh" #include "arch/sparc/faults.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" namespace SparcISA { diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc index 3fe9ce4f1..64f2d4b1d 100644 --- a/src/arch/x86/stacktrace.cc +++ b/src/arch/x86/stacktrace.cc @@ -35,7 +35,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/system.hh" namespace X86ISA diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc index ada5e27d6..0660827e9 100644 --- a/src/base/remote_gdb.cc +++ b/src/base/remote_gdb.cc @@ -146,9 +146,8 @@ #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" #include "debug/GDBAll.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/port.hh" -#include "mem/se_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/full_system.hh" #include "sim/system.hh" diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 30806a7c7..7574c4d7e 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -55,8 +55,8 @@ #include "cpu/profile.hh" #include "cpu/quiesce_event.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/se_translating_port_proxy.hh" +#include "mem/translating_port_proxy.hh" #include "params/BaseCPU.hh" #include "sim/faults.hh" #include "sim/full_system.hh" diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index 2210a7628..07176b72e 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -33,10 +33,10 @@ #include "cpu/profile.hh" #include "cpu/quiesce_event.hh" #include "kern/kernel_stats.hh" -#include "mem/fs_translating_port_proxy.hh" #include "mem/port.hh" #include "mem/port_proxy.hh" #include "mem/se_translating_port_proxy.hh" +#include "mem/translating_port_proxy.hh" #include "sim/full_system.hh" #include "sim/serialize.hh" #include "sim/system.hh" @@ -112,7 +112,7 @@ ThreadState::initMemProxies(ThreadContext *tc) baseCpu->cacheLineSize()); assert(virtProxy == NULL); - virtProxy = new FSTranslatingPortProxy(tc); + virtProxy = new TranslatingPortProxy(tc); } else { assert(virtProxy == NULL); virtProxy = new SETranslatingPortProxy( diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index df80cdc4a..dd93c68f4 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -45,9 +45,6 @@ namespace Kernel { class Checkpoint; -class FSTranslatingPortProxy; -class SETranslatingPortProxy; - /** * Struct for holding general thread state that is needed across CPU * models. This includes things such as pointers to the process, diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc index 629f162e8..a9b3f93a5 100644 --- a/src/dev/arm/gic_v3_redistributor.cc +++ b/src/dev/arm/gic_v3_redistributor.cc @@ -44,7 +44,6 @@ #include "debug/GIC.hh" #include "dev/arm/gic_v3_cpu_interface.hh" #include "dev/arm/gic_v3_distributor.hh" -#include "mem/fs_translating_port_proxy.hh" const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400, SGI_base + 0x0420); diff --git a/src/kern/linux/helpers.cc b/src/kern/linux/helpers.cc index a7c21837e..559844004 100644 --- a/src/kern/linux/helpers.cc +++ b/src/kern/linux/helpers.cc @@ -40,7 +40,7 @@ #include "arch/isa_traits.hh" #include "config/the_isa.hh" #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" #include "sim/byteswap.hh" #include "sim/system.hh" diff --git a/src/mem/SConscript b/src/mem/SConscript index d4eb4615b..f7636b235 100644 --- a/src/mem/SConscript +++ b/src/mem/SConscript @@ -81,7 +81,7 @@ Source('serial_link.cc') Source('mem_delay.cc') if env['TARGET_ISA'] != 'null': - Source('fs_translating_port_proxy.cc') + Source('translating_port_proxy.cc') Source('se_translating_port_proxy.cc') Source('page_table.cc') diff --git a/src/mem/fs_translating_port_proxy.cc b/src/mem/fs_translating_port_proxy.cc deleted file mode 100644 index 99a4b8e48..000000000 --- a/src/mem/fs_translating_port_proxy.cc +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2011,2013 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * Port object definitions. - */ - -#include "mem/fs_translating_port_proxy.hh" - -#include "base/chunk_generator.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "sim/system.hh" - -FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) : - PortProxy(tc->getCpuPtr()->getSendFunctional(), - tc->getSystemPtr()->cacheLineSize()), _tc(tc), - pageBytes(tc->getSystemPtr()->getPageBytes()) -{} - -bool -FSTranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const -{ - BaseTLB *dtb = _tc->getDTBPtr(); - BaseTLB *itb = _tc->getDTBPtr(); - return dtb->translateFunctional(req, _tc, mode) == NoFault || - itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault; -} - -bool -FSTranslatingPortProxy::tryTLBs(RequestPtr req, BaseTLB::Mode mode) const -{ - // If at first this doesn't succeed, try to fixup and translate again. If - // it still fails, report failure. - return tryTLBsOnce(req, mode) || - (fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode)); -} - -bool -FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const -{ - for (ChunkGenerator gen(addr, size, pageBytes); !gen.done(); - gen.next()) - { - auto req = std::make_shared( - gen.addr(), gen.size(), 0, Request::funcMasterId, 0, - _tc->contextId()); - - if (!tryTLBs(req, BaseTLB::Read)) - return false; - - PortProxy::readBlobPhys( - req->getPaddr(), req->getFlags(), p, gen.size()); - - p = static_cast(p) + gen.size(); - } - return true; -} - -bool -FSTranslatingPortProxy::tryWriteBlob( - Addr addr, const void *p, int size) const -{ - for (ChunkGenerator gen(addr, size, pageBytes); !gen.done(); - gen.next()) - { - auto req = std::make_shared( - gen.addr(), gen.size(), 0, Request::funcMasterId, 0, - _tc->contextId()); - - if (!tryTLBs(req, BaseTLB::Write)) - return false; - - PortProxy::writeBlobPhys( - req->getPaddr(), req->getFlags(), p, gen.size()); - p = static_cast(p) + gen.size(); - } - return true; -} - -bool -FSTranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size) const -{ - for (ChunkGenerator gen(address, size, pageBytes); !gen.done(); - gen.next()) - { - auto req = std::make_shared( - gen.addr(), gen.size(), 0, Request::funcMasterId, 0, - _tc->contextId()); - - if (!tryTLBs(req, BaseTLB::Write)) - return false; - - PortProxy::memsetBlobPhys( - req->getPaddr(), req->getFlags(), v, gen.size()); - } - return true; -} diff --git a/src/mem/fs_translating_port_proxy.hh b/src/mem/fs_translating_port_proxy.hh deleted file mode 100644 index c3f1bc6eb..000000000 --- a/src/mem/fs_translating_port_proxy.hh +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2011 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file - * TranslatingPortProxy Object Declaration for FS. - * - * Port proxies are used when non structural entities need access to - * the memory system. Proxy objects replace the previous - * FunctionalPort, TranslatingPort and VirtualPort objects, which - * provided the same functionality as the proxies, but were instances - * of ports not corresponding to real structural ports of the - * simulated system. Via the port proxies all the accesses go through - * an actual port and thus are transparent to a potentially - * distributed memory and automatically adhere to the memory map of - * the system. - */ - -#ifndef __MEM_FS_TRANSLATING_PORT_PROXY_HH__ -#define __MEM_FS_TRANSLATING_PORT_PROXY_HH__ - -#include "arch/generic/tlb.hh" -#include "mem/port_proxy.hh" - -class ThreadContext; - -/** - * This proxy attempts to translate virtual addresses using the TLBs. If it - * fails, subclasses can override the fixupAddr virtual method to try to - * recover, and then attempt the translation again. If it still fails then the - * access as a whole fails. - */ -class FSTranslatingPortProxy : public PortProxy -{ - private: - bool tryTLBsOnce(RequestPtr req, BaseTLB::Mode) const; - bool tryTLBs(RequestPtr req, BaseTLB::Mode) const; - - protected: - ThreadContext* _tc; - const Addr pageBytes; - - virtual bool - fixupAddr(Addr addr, BaseTLB::Mode mode) const - { - return false; - } - - public: - - FSTranslatingPortProxy(ThreadContext* tc); - ~FSTranslatingPortProxy() {} - - /** Version of tryReadblob that translates virt->phys and deals - * with page boundries. */ - bool tryReadBlob(Addr addr, void *p, int size) const override; - - /** Version of tryWriteBlob that translates virt->phys and deals - * with page boundries. */ - bool tryWriteBlob(Addr addr, const void *p, int size) const override; - - /** - * Fill size bytes starting at addr with byte value val. - */ - bool tryMemsetBlob(Addr address, uint8_t v, int size) const override; -}; - -#endif //__MEM_FS_TRANSLATING_PORT_PROXY_HH__ diff --git a/src/mem/se_translating_port_proxy.cc b/src/mem/se_translating_port_proxy.cc index 8bab243cb..458b2fad5 100644 --- a/src/mem/se_translating_port_proxy.cc +++ b/src/mem/se_translating_port_proxy.cc @@ -44,8 +44,8 @@ #include "sim/system.hh" SETranslatingPortProxy::SETranslatingPortProxy( - ThreadContext *tc, AllocType alloc) - : FSTranslatingPortProxy(tc), allocating(alloc) + ThreadContext *tc, AllocType alloc) : + TranslatingPortProxy(tc), allocating(alloc) {} bool diff --git a/src/mem/se_translating_port_proxy.hh b/src/mem/se_translating_port_proxy.hh index 96e17714c..1b6be8a25 100644 --- a/src/mem/se_translating_port_proxy.hh +++ b/src/mem/se_translating_port_proxy.hh @@ -41,9 +41,9 @@ #ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__ #define __MEM_SE_TRANSLATING_PORT_PROXY_HH__ -#include "mem/fs_translating_port_proxy.hh" +#include "mem/translating_port_proxy.hh" -class SETranslatingPortProxy : public FSTranslatingPortProxy +class SETranslatingPortProxy : public TranslatingPortProxy { public: diff --git a/src/mem/translating_port_proxy.cc b/src/mem/translating_port_proxy.cc new file mode 100644 index 000000000..c44ff5fca --- /dev/null +++ b/src/mem/translating_port_proxy.cc @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2011,2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file + * Port object definitions. + */ + +#include "mem/translating_port_proxy.hh" + +#include "base/chunk_generator.hh" +#include "cpu/base.hh" +#include "cpu/thread_context.hh" +#include "sim/system.hh" + +TranslatingPortProxy::TranslatingPortProxy(ThreadContext *tc) : + PortProxy(tc->getCpuPtr()->getSendFunctional(), + tc->getSystemPtr()->cacheLineSize()), _tc(tc), + pageBytes(tc->getSystemPtr()->getPageBytes()) +{} + +bool +TranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const +{ + BaseTLB *dtb = _tc->getDTBPtr(); + BaseTLB *itb = _tc->getDTBPtr(); + return dtb->translateFunctional(req, _tc, mode) == NoFault || + itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault; +} + +bool +TranslatingPortProxy::tryTLBs(RequestPtr req, BaseTLB::Mode mode) const +{ + // If at first this doesn't succeed, try to fixup and translate again. If + // it still fails, report failure. + return tryTLBsOnce(req, mode) || + (fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode)); +} + +bool +TranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const +{ + for (ChunkGenerator gen(addr, size, pageBytes); !gen.done(); + gen.next()) + { + auto req = std::make_shared( + gen.addr(), gen.size(), 0, Request::funcMasterId, 0, + _tc->contextId()); + + if (!tryTLBs(req, BaseTLB::Read)) + return false; + + PortProxy::readBlobPhys( + req->getPaddr(), req->getFlags(), p, gen.size()); + + p = static_cast(p) + gen.size(); + } + return true; +} + +bool +TranslatingPortProxy::tryWriteBlob( + Addr addr, const void *p, int size) const +{ + for (ChunkGenerator gen(addr, size, pageBytes); !gen.done(); + gen.next()) + { + auto req = std::make_shared( + gen.addr(), gen.size(), 0, Request::funcMasterId, 0, + _tc->contextId()); + + if (!tryTLBs(req, BaseTLB::Write)) + return false; + + PortProxy::writeBlobPhys( + req->getPaddr(), req->getFlags(), p, gen.size()); + p = static_cast(p) + gen.size(); + } + return true; +} + +bool +TranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size) const +{ + for (ChunkGenerator gen(address, size, pageBytes); !gen.done(); + gen.next()) + { + auto req = std::make_shared( + gen.addr(), gen.size(), 0, Request::funcMasterId, 0, + _tc->contextId()); + + if (!tryTLBs(req, BaseTLB::Write)) + return false; + + PortProxy::memsetBlobPhys( + req->getPaddr(), req->getFlags(), v, gen.size()); + } + return true; +} diff --git a/src/mem/translating_port_proxy.hh b/src/mem/translating_port_proxy.hh new file mode 100644 index 000000000..1e17c64be --- /dev/null +++ b/src/mem/translating_port_proxy.hh @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2011 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEM_TRANSLATING_PORT_PROXY_HH__ +#define __MEM_TRANSLATING_PORT_PROXY_HH__ + +#include "arch/generic/tlb.hh" +#include "mem/port_proxy.hh" + +class ThreadContext; + +/** + * This proxy attempts to translate virtual addresses using the TLBs. If it + * fails, subclasses can override the fixupAddr virtual method to try to + * recover, and then attempt the translation again. If it still fails then the + * access as a whole fails. + */ +class TranslatingPortProxy : public PortProxy +{ + private: + bool tryTLBsOnce(RequestPtr req, BaseTLB::Mode) const; + bool tryTLBs(RequestPtr req, BaseTLB::Mode) const; + + protected: + ThreadContext* _tc; + const Addr pageBytes; + + virtual bool + fixupAddr(Addr addr, BaseTLB::Mode mode) const + { + return false; + } + + public: + + TranslatingPortProxy(ThreadContext* tc); + + /** Version of tryReadblob that translates virt->phys and deals + * with page boundries. */ + bool tryReadBlob(Addr addr, void *p, int size) const override; + + /** Version of tryWriteBlob that translates virt->phys and deals + * with page boundries. */ + bool tryWriteBlob(Addr addr, const void *p, int size) const override; + + /** + * Fill size bytes starting at addr with byte value val. + */ + bool tryMemsetBlob(Addr address, uint8_t v, int size) const override; +}; + +#endif //__MEM_TRANSLATING_PORT_PROXY_HH__ diff --git a/src/sim/arguments.hh b/src/sim/arguments.hh index da7a8edce..2861e4dd6 100644 --- a/src/sim/arguments.hh +++ b/src/sim/arguments.hh @@ -33,7 +33,7 @@ #include #include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" class Arguments { diff --git a/src/sim/vptr.hh b/src/sim/vptr.hh index d1ec32af6..92aea797c 100644 --- a/src/sim/vptr.hh +++ b/src/sim/vptr.hh @@ -29,7 +29,7 @@ #ifndef __SIM_VPTR_HH__ #define __SIM_VPTR_HH__ -#include "mem/fs_translating_port_proxy.hh" +#include "mem/port_proxy.hh" class ThreadContext;