From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Apr 2022 10:07:15 +0000 (+0200)
Subject: Preserve internal wires for external nets
X-Git-Tag: yosys-0.16~8^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a1f529099d7108e26e5598b1879b2b8183e4ec7;p=yosys.git

Preserve internal wires for external nets
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b30a5baa0..44196a310 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2041,7 +2041,7 @@ struct VerificExtNets
 			string name = stringf("___extnets_%d", portname_cnt++);
 			Port *new_port = new Port(name.c_str(), drive_up ? DIR_OUT : DIR_IN);
 			nl->Add(new_port);
-			net->Connect(new_port);
+			nl->Buf(net)->Connect(new_port);
 
 			// create new Net in up Netlist
 			Net *new_net = final_net;