From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 9 Sep 2022 18:23:52 +0000 (+0100)
Subject: hooray got test_pysvp64dis.py working with new Verbosity level
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a2a6df22531a9009c960da0183508e4ffbec12d;p=openpower-isa.git

hooray got test_pysvp64dis.py working with new Verbosity level
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index f25659d2..61f83366 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -1,6 +1,7 @@
 from openpower.simulator.program import Program
 from openpower.sv.trans.pysvp64dis import load, dump
 from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.decoder.power_insn import Verbosity
 import unittest
 import sys
 
@@ -39,7 +40,7 @@ class SVSTATETestCase(unittest.TestCase):
                 #print ("insn", insn)
             insns = list(insns)
             print ("insns", insns)
-            for i, line in enumerate(dump(insns, verbose=False, short=True)):
+            for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
                 print("instruction", repr(line), repr(expected[i]))
                 self.assertEqual(expected[i], line,
                                  "instruction %i do not match "