From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 23 Sep 2014 10:01:57 +0000 (+0200)
Subject: fill GTXE2_COMMON constants parameters and signals for SATA / disconnect unused outpu... 
X-Git-Tag: 24jan2021_ls180~2572^2~215
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a5a2d10e32ef132359c495ba4d88a3c77c022a1;p=litex.git

fill GTXE2_COMMON constants parameters and signals for SATA / disconnect unused output ports
---

diff --git a/lib/sata/k7sataphy.py b/lib/sata/k7sataphy.py
index 086dfb16..bdff48f0 100644
--- a/lib/sata/k7sataphy.py
+++ b/lib/sata/k7sataphy.py
@@ -651,67 +651,67 @@ class K7SATAPHY(Module):
 		Instance("GTXE2_COMMON",
 			# Simulation attributes
 				p_SIM_RESET_SPEEDUP=,
-				p_SIM_QPLLREFCLK_SEL=,
+				p_SIM_QPLLREFCLK_SEL=0b001,
 				p_SIM_VERSION=,
 
 			# Common block attributes
-				p_BIAS_CFG=,
-				p_COMMON_CFG=,
-				p_QPLL_CFG=,
-				p_QPLL_CLKOUT_CFG=,
-				p_QPLL_COARSE_FREQ_OVRD=,
-				p_QPLL_COARSE_FREQ_OVRD_EN=,
-				p_QPLL_CP=,
-				p_QPLL_CP_MONITOR_EN=,
-				p_QPLL_DMONITOR_SEL=,
+				p_BIAS_CFG=0x0000040000001000,
+				p_COMMON_CFG=0,
+				p_QPLL_CFG=0x06801c1,
+				p_QPLL_CLKOUT_CFG=0,
+				p_QPLL_COARSE_FREQ_OVRD=0b010000,
+				p_QPLL_COARSE_FREQ_OVRD_EN=0,
+				p_QPLL_CP=0b0000011111,
+				p_QPLL_CP_MONITOR_EN=0,
+				p_QPLL_DMONITOR_SEL=0,
 				p_QPLL_FBDIV=,
 				p_QPLL_FBDIV_MONITOR_EN=,
 				p_QPLL_FBDIV_RATIO=,
-				p_QPLL_INIT_CFG=,
-				p_QPLL_LOCK_CFG=,
-				p_QPLL_LPF=,
-				p_QPLL_REFCLK_DIV=,
+				p_QPLL_INIT_CFG=0x000006,
+				p_QPLL_LOCK_CFG=0x21e9,
+				p_QPLL_LPF=0b1111,
+				p_QPLL_REFCLK_DIV=1,
 
 			# Common block - Dynamic Reconfiguration Port (DRP)
-				i_DRPADDR=,
-				i_DRPCLK=,
-				i_DRPDI=,
-				o_DRPDO=,
-				i_DRPEN=,
-				o_DRPRDY=,
-				i_DRPWE=,
+				i_DRPADDR=0,
+				i_DRPCLK=0,
+				i_DRPDI=0,
+				#o_DRPDO=,
+				i_DRPEN=0,
+				#o_DRPRDY=,
+				i_DRPWE=0,
 
 			# Common block  - Ref Clock Ports
-				i_GTGREFCLK=,
-				i_GTNORTHREFCLK0=,
-				i_GTNORTHREFCLK1=,
+				i_GTGREFCLK=0,
+				i_GTNORTHREFCLK0=0,
+				i_GTNORTHREFCLK1=0,
 				i_GTREFCLK0=,
-				i_GTREFCLK1=,
-				i_GTSOUTHREFCLK0=,
-				i_GTSOUTHREFCLK1=,
+				i_GTREFCLK1=0,
+				i_GTSOUTHREFCLK0=0,
+				i_GTSOUTHREFCLK1=0,
 
 			# Common block - QPLL Ports
-				o_QPLLDMONITOR=,
-				o_QPLLFBCLKLOST=,
-				o_QPLLLOCK=,
-				i_QPLLLOCKDETCLK=,
-				i_QPLLLOCKEN=,
+				#o_QPLLDMONITOR=,
+				#o_QPLLFBCLKLOST=,
+				#o_QPLLLOCK=,
+				i_QPLLLOCKDETCLK=0,
+				i_QPLLLOCKEN=1,
 				o_QPLLOUTCLK=,
 				o_QPLLOUTREFCLK=,
-				i_QPLLOUTRESET=,
-				i_QPLLPD=,
-				o_QPLLREFCLKLOST=,
-				i_QPLLREFCLKSEL=,
-				i_QPLLRESET=,
-				i_QPLLRSVD1=,
-				i_QPLLRSVD2=,
-				o_REFCLKOUTMONITOR=,
+				i_QPLLOUTRESET=0,
+				i_QPLLPD=0,
+				#o_QPLLREFCLKLOST=,
+				i_QPLLREFCLKSEL=0b001,
+				i_QPLLRESET=0,
+				i_QPLLRSVD1=0,
+				i_QPLLRSVD2=_ones(5),
+				#o_REFCLKOUTMONITOR=,
 
 			# Common block Ports
-				i_BGBYPASSB=,
-				i_BGMONITORENB=,
-				i_BGPDB=,
-				i_BGRCALOVRD=,
-				i_PMARSVD=,
-				i_RCALENB=
+				i_BGBYPASSB=1,
+				i_BGMONITORENB=1,
+				i_BGPDB=1,
+				i_BGRCALOVRD=0,
+				i_PMARSVD=0,
+				i_RCALENB=1
 		)