From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 May 2021 17:33:36 +0000 (+0100)
Subject: whoops must include SVSTATE in STATE regfile regspec read/write map
X-Git-Tag: 0.0.3~85
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a6a0f7bc9bd1d36f62166c3458906864dc31802;p=openpower-isa.git

whoops must include SVSTATE in STATE regfile regspec read/write map
---

diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index eee04967..c55ffe61 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -92,10 +92,13 @@ def regspec_decode_read(e, regfile, name):
         # STATE register numbering is *unary* encoded
         PC = 1<<StateRegsEnum.PC
         MSR = 1<<StateRegsEnum.MSR
+        SVSTATE = 1<<StateRegsEnum.SVSTATE
         if name in ['cia', 'nia']:
             return Const(1), PC # TODO: detect read-conditions
         if name == 'msr':
             return Const(1), MSR # TODO: detect read-conditions
+        if name == 'svstate':
+            return Const(1), SVSTATE # TODO: detect read-conditions
 
     # FAST regfile
 
@@ -161,10 +164,13 @@ def regspec_decode_write(e, regfile, name):
         # STATE register numbering is *unary* encoded
         PC = 1<<StateRegsEnum.PC
         MSR = 1<<StateRegsEnum.MSR
+        SVSTATE = 1<<StateRegsEnum.SVSTATE
         if name in ['cia', 'nia']:
             return None, PC # hmmm
         if name == 'msr':
             return None, MSR # hmmm
+        if name == 'svstate':
+            return None, SVSTATE # hmmm
 
     # FAST regfile