From: whitequark <whitequark@whitequark.org>
Date: Tue, 20 Jul 2021 10:30:39 +0000 (+0000)
Subject: cxxrtl: treat wires with multiple defs as not inlinable.
X-Git-Tag: yosys-0.10~92^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a6ddf78921290851ca7bbe7605d9e146055dc39;p=yosys.git

cxxrtl: treat wires with multiple defs as not inlinable.

Fixes #2883.
---

diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 56305258a..46759e8fa 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -326,8 +326,14 @@ struct FlowGraph {
 		for (auto bit : sig.bits())
 			bit_has_state[bit] |= is_ff;
 		// Only comb defs of an entire wire in the right order can be inlined.
-		if (!is_ff && sig.is_wire())
-			wire_def_inlinable[sig.as_wire()] = inlinable;
+		if (!is_ff && sig.is_wire()) {
+			// Only a single def of a wire can be inlined. (Multiple defs of a wire are unsound, but we
+			// handle them anyway to avoid assertion failures later.)
+			if (!wire_def_inlinable.count(sig.as_wire()))
+				wire_def_inlinable[sig.as_wire()] = inlinable;
+			else
+				wire_def_inlinable[sig.as_wire()] = false;
+		}
 	}
 
 	void add_uses(Node *node, const RTLIL::SigSpec &sig)