From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 10:29:00 +0000 (+0100)
Subject: invert SPR1/2 in branch output data
X-Git-Tag: div_pipeline~695
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1a972d0f7d050692b4a622e78893832d1cf7082e;p=soc.git

invert SPR1/2 in branch output data
---

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index f32872b1..78cab605 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -74,8 +74,8 @@ class BranchOutputData(IntegerData):
         self.nia = Data(64, name="nia")
 
         # convenience variables.
-        self.lr = self.tar = self.spr1
-        self.ctr = self.spr2
+        self.ctr = self.spr1
+        self.lr = self.tar = self.spr2
 
     def __iter__(self):
         yield from super().__iter__()