From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 14 Oct 2021 11:04:32 +0000 (+0200)
Subject: Support PRIM_BUFIF1 primitive
X-Git-Tag: yosys-0.11~44^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1aa68969660549ae9c0fd683c0a328c499694b49;p=yosys.git

Support PRIM_BUFIF1 primitive
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 74638dc8d..fcacbd086 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -371,7 +371,7 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
-	if (inst->Type() == PRIM_TRI) {
+	if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
 		module->addMuxGate(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
 		return true;
 	}
@@ -497,7 +497,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		return true;
 	}
 
-	if (inst->Type() == PRIM_TRI) {
+	if ((inst->Type() == PRIM_TRI) || (inst->Type() == PRIM_BUFIF1)) {
 		cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
 		import_attributes(cell->attributes, inst);
 		return true;