From: Staf Verhaegen <staf@fibraservi.eu>
Date: Thu, 26 Mar 2020 12:31:38 +0000 (+0100)
Subject: Re: [libre-riscv-dev] cache SRAM organisation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1aa846282682a085fe5ff7e9eff6a2c69b0c0226;p=libre-riscv-dev.git

Re: [libre-riscv-dev] cache SRAM organisation
---

diff --git a/5d/832a18daf516839bee02cfbd1e355da6966e09 b/5d/832a18daf516839bee02cfbd1e355da6966e09
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+From: Staf Verhaegen <staf@fibraservi.eu>
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Thu, 26 Mar 2020 13:31:38 +0100
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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+(Sorry send to early)
+
+
+> .In theory on a single port SRAM
+
+In theory on a single port SRAM the write data input and the Q data output =
+could be on opposite sides of the block but I will make sure that these pin=
+s are on the same side of the block and close together so you don't need mu=
+ch wire to connect a pass-through MUX.
+
+greets,
+Staf.
+
+
+
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