From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 00:43:29 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1abe93e48d8bb78cd0753d46dfbe1885a1e803eb;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

1abe93e48d8bb78cd0753d46dfbe1885a1e803eb
diff --cc CHANGELOG
index f7a6e9758,496a521be..192fc5a8d
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -16,14 -16,10 +16,15 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
 +    - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
  
  
  Yosys 0.7 .. Yosys 0.8