From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 14 Oct 2018 05:26:45 +0000 (+0100)
Subject: blt and use of rv_add
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ac4d9243d3e08b849b7739bdb46735342f5874e;p=riscv-isa-sim.git

blt and use of rv_add
---

diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index c54fb76..85b0be6 100644
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(RS1) < sreg_t(RS2))
+if(rv_lt(sreg_t(RS1), sreg_t(RS2)))
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index ff75e8a..d1d6b31 100644
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(RS1 < RS2)
+if(rv_lt(RS1, RS2))
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 0f0999c..61e44da 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));
+WRITE_RD(MMU.load_int8(rv_add(RS1, insn.i_imm())));
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 64d4a68..2165875 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm()));
+WRITE_RD(MMU.load_uint8(rv_add(RS1, insn.i_imm())));
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 1122b98..6349603 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(MMU.load_int64(RS1 + insn.i_imm()));
+WRITE_RD(MMU.load_int64(rv_add(RS1, insn.i_imm())));
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 4e8ed04..45e082a 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int32(RS1 + insn.i_imm()));
+WRITE_RD(MMU.load_int32(rv_add(RS1, insn.i_imm())));