From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 22 May 2020 17:51:08 +0000 (+0100)
Subject: div probably uses ALU not Logical, needs double-checking though
X-Git-Tag: div_pipeline~938
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1aca708a10492637b144adc79a9351c37add6f0a;p=soc.git

div probably uses ALU not Logical, needs double-checking though
---

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index e634a505..52ac0d92 100644
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -1,10 +1,10 @@
 from nmigen import Signal, Const
 from soc.fu.pipe_data import IntegerData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
-from soc.fu.logical.pipe_data import LogicalInputData
+from soc.fu.alu.pipe_data import ALUInputData # TODO: check this
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 class DivPipeSpec(CommonPipeSpec):
-    regspec = (LogicalInputData.regspec, ALUOutputData.regspec)
+    regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompLogicalOpSubset