From: Ivan Grokhotkov <ivan@espressif.com>
Date: Mon, 8 Jun 2020 21:17:11 +0000 (+0200)
Subject: [breaking-change] blackice: remove UART RTS/CTS signals.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1acda441f977c61ab0a7e1edad563d8cefc52252;p=nmigen-boards.git

[breaking-change] blackice: remove UART RTS/CTS signals.

According to the schematic, RTS and CTS are not connected to CH340G in
this version of the board.

Ref. https://github.com/monsonite/BackIce_FPGA/blob/master/BlackIce18_07_01D.pdf
and https://forum.mystorm.uk/uploads/default/original/1X/a5db1ce1c9bc2d91e63cfdc8424d699c2419a3d0.png
---

diff --git a/nmigen_boards/blackice.py b/nmigen_boards/blackice.py
index 75c9ac9..5853fe4 100644
--- a/nmigen_boards/blackice.py
+++ b/nmigen_boards/blackice.py
@@ -28,8 +28,9 @@ class BlackIcePlatform(LatticeICE40Platform):
         *SwitchResources(pins="37 38 39 41", invert=True, attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
 
         UARTResource(0,
-            rx="88", tx="85", rts="91", cts="94",
-            attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)
+            rx="88", tx="85",
+            attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1),
+            role="dce"
         ),
 
         SRAMResource(0,