From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Tue, 19 Apr 2022 17:43:41 +0000 (+0000)
Subject: isa.caller: support whole integer pseudo-field
X-Git-Tag: sv_maxu_works-initial~492
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1ace38c5523c231a500500b4942433ddadc1d707;p=openpower-isa.git

isa.caller: support whole integer pseudo-field
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 4838de0c..a55023ef 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -263,6 +263,7 @@ class SVP64RMFields(SelectableIntMapping):
     def __init__(self, value=0):
         self.spr = SelectableInt(value=value, bits=24)
         return super().__init__(si=self.spr, fields={
+            "spr": range(24),
             # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
             "mmode": (0,),
             "mask": range(1, 4),
@@ -304,6 +305,7 @@ class SVP64PrefixFields(SelectableIntMapping):
     def __init__(self):
         self.insn = SelectableInt(0, 32)
         return super().__init__(si=self.insn, fields={
+            "insn": range(32),
             # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
             "major": range(0, 6),
             "pid": (7, 9),